The present disclosure relates to phase frequency detectors, and more particularly, to phase frequency detectors having limited output pulse width.
Phase-locked loop (PLL) can be applied in a variety of applications, such as clock/data recovery, frequency or phase modulation/demodulation, and generating clocks with stable frequency. In general, a conventional PLL includes a phase frequency detector (PFD) for detecting phase difference and frequency difference between a reference signal and a feedback signal; a charge-pump for generating an output current according to the detection result of the PFD; and a loop filter for adjusting the operation of a voltage-controlled oscillator (VCO) according to the output current until the frequency and phase of the feedback signal match that of the reference signal.
Typically, the loop bandwidth of the conventional PLL is designed one order of magnitude less than the frequency of the reference signal in order to maintain the loop stability. As the frequency of the reference signal decreases, the loop bandwidth of the PLL should be lowered correspondingly. In such a scheme, a large capacitor is required by the loop filter to suppress the jitter of the VCO. As a result, the circuitry area and volume is significantly increased.